Achronix Speedster22i User Macro Guide Manuale Utente Scaricare il pdf (Pagina 88)

Registers DFFNES

Speedster22i Macro Cell Library

AchronixSemiconductorProprietary PAGE 72

DFFNES

Negative Clock Edge D-Type Register with Clock Enable and

Asynchronous/Synchronous Set

ckn

DFFNES

Figure 2-11: Logic Symbol

DFFNES is a si

ngle D ‐type register with data  input (d), clock enable (ce), clock (ckn), and

active‐low set (sn) inputs and data (q) output. The active‐low set inpu t overrides all other

inputswhenitis assertedlowand setsthedata output high.The resonseof theq outputin

sponsetotheassertedsetdependsonthevalueofthesr_assertionparameterandisdetailed

in Table 2‐36

: DFFNES Function Table when sr_assertion = “unclocked” and Table

2‐37: DFFNESFunctionTablewhensr_assertion=“clocked”.Ifth

esetinputisnotasserted,

thedataoutputissettoth

evalueonthedatainputuponthenextfallingedgeoftheclockif

theactive‐highclockenableinputisasserted.

Pins

Table 2-34: Pin Descriptions

Name Type Description

d Data input.

Active-low asynchronous/

synchronous set input. A low on sn sets the q

output high independent of the other inputs if the sr_assertion parameter

is set to “unclocked”. If the sr_assertion parameter is set to “clocked”, a low

on sn sets the q output high at the next falling edge of the clock.

ce Active-high clock enable input.

ckn Negative-edge clock input.

Data output. The value pr

esent on the data input is transferred to the q

output upon the falling edge of the clock if the clock enable input is high

and the set input is high.

Parameters

Table 2-35: Parameters

Parameter Defined Values Default Value

init 1’b1

sr_assertion “unclocked”

init

TheinitparameterdefinestheinitialvalueoftheoutputoftheDFFNESregister.Thisisthe

valuetheregistertakesupontheinitialapplicationofpowertotheFPGA.Thedefaultvalue

oftheinitparameteris1’b1.

input

output

1’b0, 1’b1

“unclocked”, “clocked”

1 2 ... 83 84 85 86 87 88 89 90 91 92 93 ... 223 224

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