Achronix Speedster22i User Macro Guide Manuale Utente Scaricare il pdf (Pagina 213)

PLL/DLL Clock Generators ACX_CLKGEN

Speedster Macro Cell Library

www.achronix.com PAGE 196

Mixed Feedback Mode

Mixed Feedback mode should only be used in the case that the  output divider range is not

enough.TheVCOisdividedbytheoutputdividerinsideoneofthephaserotators.Theclkout

outputofthePLL,afterithas beensentthroughtheclocknetwork,isfedbackto

thePLLfor

deskewing.The feedbackclock is senttotheFeedback Dividerbefore it is sentto thePhase

FrequencyDetector.OnlyintegermodeoftheFeedbackDividershouldbeusedinthismode.

TheVCOfrequencyisrelatedtothereferenceclockfrequencythroughtherelationship:

VCO

=(Q*N*P/M)*F

ref

PLL Control

ThedefaultcontroloftheACX_CLKGENblockisbyusing acombination ofthepinsandthe

user‐defined parameters. It is recommended that the user configure the ACX_CLKGEN

modulefromwithinthe ACEGUIsoftware.Usingthe ACEGUItoconfigure thePLLhasthe

addedbenefitforcross‐checking

theparametersforlegal combinationsandensuringthatthe

VCO has been configured to operate within the 1000‐2000 MHz range. Once the user has

generatedaGUI‐basedVerilogorVHDLwrapper,hemay latermodify thesettingsdirectly

withinthewrapperorgobacktotheGUIand

haveitregeneratethewrapper.Usersmayalter‐

nativelychoosetoinstantiatetheACX_CLKGENmoduledirectlyintotheirRTLcode.

Resetting the PLL

TheuserisnotrequiredtomanuallyresetthePLL.TheFPGAConfiguration Controllerwaits

for allofthe userclockstostabilize before putting the FPGA into user mode.Asaminimal

configuration,the user may tie the rstn inpu t high to keep it inactive.Theuseralso has the



choicetomanuallyresetthePLLbyassertingtherstninputlow.Theusermustassertrstnlow

foratleastonecycleoftheclockfrequencyinputintothePhaseFrequencyDetector(afterthe

Reference Divider). After the rstn is deasserted, the pll_lock will go high within 500 refclk

(aftertheReferenceDivider)clockperiodsifthePLLisusedinintegerdividermodeand1000

clockperiodsifthePLLisusedinfractionaldividermode.

Serial Control Bus (SCB)

The ACX_CLKGEN module also allows the user to control the PLL from the Serial Control

Bus(SCB)interface.Uponinitialpower‐upoftheFPGA,thePLLoperatesbasedonthevalues

oftheparameters.Theparametersdefine theinitialbehavioroftheACX_CLKGENmodule.

Theusermayoptionallyswitchcontrol

oftheACX_CLKGENtothe ControlStatusRegisters

(CSR),whichareaccessedviatheSCBinterface.ControlisswitchedtotheCSRbysettingthe

csr_enablebit(CSRAddress1C,bit0)high.Afterthecsr_enablebitisenabled,theusermay

modify the behavior of the various components within

the ACX_CLKGEN module

dynamicallyfromtheFPGAfabric.

Table9‐4definestheregisterswithintheCSR.

Chapter9–“SerialControlBusReadOperation”showsthetimingforaSerialControlBus

readoperationwhileChapter9–“SerialControlBusWriteOperation”showsthetimingfor

theSerialControlBuswriteoperation.IftheuserpreferstointerfacewithCSRregisterswitha

parallel interface, he may choose to instantiate an ACX_SBUS_MASTER from the Achronix

Macro Library into the design. Note that the internal register file of the ACX_CLKGEN

moduleisimplementedasa32‐bitinterface

withonlythebottom8bitsareused.

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Achronix Speedster22i User Macro Guide Manuale Utente Pagina 213

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