Achronix Speedster22i User Macro Guide Manuale Utente Scaricare il pdf (Pagina 82)

Registers DFFNEC

Speedster22i Macro Cell Library

AchronixSemiconductorProprietary PAGE 66

Table 2-26: Function Table

Inputs Output

cn ce d ckn q



Verilog Instantiation Template

DFFNEC #(.init(1’b0))

instance_name

(.q(user_out),

.d(user_din),

.cn(user_clear),

.ce(user_clock_enable),

.ckn(user_clock));

VHDL Instantiation Template

------------- ACHRONIX LIBRARY ------------

library speedster22i;

use speedster22i.components.all;

------------- DONE ACHRONIX LIBRARY ---------

-- Component Instantiation

DFFNEC_instance_name : DFFNEC

generic map ( init => ‘0’)

port map (q => user_out,

d => user_din,

cn => user_clear,

ce => user_clock_enable,

ckn => user_clock);

X0XXHold

01X 0

0 0

1 1

1 2 ... 77 78 79 80 81 82 83 84 85 86 87 ... 223 224

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Achronix Speedster22i User Macro Guide Manuale Utente Pagina 82