
I/O Cells IPAD_D
Speedster Macro Cell Library
www.achronix.com PAGE 16
Table 1-19: Input Function table
pad rxdata_en rxclk dout
Verilog Instantiation Template
IPAD_D #( .location(""),
.iostandard("LVCMOS18"),
.rstmode("async"),
.rstvalue("low"),
.keepmode("none"),
.hysteresis("none"),
.pvt_comp("none"),
.termination("50"),
.odt("off"))
instance_name (.pad(user_pad),
.dout(user_dout),
.rstn(user_rstn),
.data_en(user_data_en),
.clk(user_clk));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
IPAD_D_instance_name : IPAD_D
generic map (location => ““,
iostandard => “LVCMOS18”,
rstmode => “async”,
rstvalue => “low”,
keepmode => “none”,
hysteresis => "none",
pvt_comp => "none",
termination => "50",
odt => "off")
port map (dout => user_dout,
pad => user_pad,
clk => user_clk,
data_en => user_data_en,
rstn => user_rstn);
01 0
11 1
X1 X
Z1 X
X,Z 0 Hold previous data
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