
I/O Cells TPAD
Speedster Macro Cell Library
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TPAD
Non-Registered Tristate Output Pad
Figure 1-22: TPAD Logic Symbol
TPADisannon‐registeredt
ristateoutputpad.
Table 1-48: Ports
Name Type Description
din Data input.
oe
Output Enbale. T
he data at the din input is driven to the pad output when
the oe input is driven high. The pad output will be driven into high-
impedance mode when oe is low.
pad Device output pad.
Table 1-49: Parameters
Parameter Defined Values Default Value
location
iostandard “LVCMOS18”
drive
slew
open_drain “true”, “false” “false”
keepmode “pullup”, “pulldown”, “none” “none”
pvt_comp “none”, “own” “none”
Table 1-50: Output Function Table
din oe pad
Verilog Instantiation Template
TPAD #(.location(""),
.iostandard("LVCMOS18"),
.drive("16"),
.slew("slow"),
.open_drain(“false”),
.keepmode(“none”),
.pvt_comp("none"))
instance_name (.din(user_din), .oe(user_oe),
.pad(user_pad));
input
input
output
“<pad_location>” ““
See Table1‐1
"2", "4", "6", "8", "12", "16" "16"
“fast”, “slow” “slow”
01 0
11
1
X0 Z
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