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Registers DFFER

Speedster22i Macro Cell Library

AchronixSemiconductorProprietary PAGE 58

sr_assertion

The sr_assertion parameter defines the behavior of the output when the rn reset input is

asserted.Assigningthesr_assertionto“unclocked”resultsinanasychronousassertionofthe

reset signal, where the q output is set to zero upon assertion of the active‐low reset signal. 

Assigningthesr_assertionto“clocked”re

sultsinasynchronousassertionoftheresetsignal,

wheretheqoutp utissettozeroat thenextrisingedgeoftheclock.Thedefault valueofthe

sr_assertionparameteris“unclocked”.

Table 2-15: DFFER Function Table when sr_assertion = “unclocked”

Inputs Output

rn ce d ck q



Table 2-16: DFFER Function Table when sr_asser

tion = “clocked”

Inputs Output

rn ce d ck q



Verilog Instantiation Template

DFFER #(.init(1’b0),

.sr_assertion(“unclocked”))

instance_name

(.q(user_out),

.d(user_din),

.rn(user_reset),

.ce(user_clock_enable),

.ck(user_clock));

0X X X 0

10 X XHold

11 0 0

1 1

0X X  0

X XHold

11 0 0

1 1

1 2 ... 69 70 71 72 73 74 75 76 77 78 79 ... 223 224

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Achronix Speedster22i User Macro Guide Manuale Utente Pagina 74