Achronix Speedster22i User Macro Guide Manuale Utente Pagina 143
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Memories BRAM80KFIFO
Speedster22i Macro Cell Library
AchronixSemiconductorProprietary PAGE 126
Table 6-25: Relationship of reg_srval bit positions to dout,doutp,doutpx
read_width
doutpx
reg_srval[39:36]
doutp
re
g_srval[35:32]
dout
reg_srval[31:0]
40 user_srval[39:36] user_srval[35:32] user_srval[31:0]
36 4’hx user_srval[35:32] user_srval[31:0]
32 4’hx 4’hx user_srval[31:0]
20 2’bxx,user_srval[19:18] 2’bxx,user_srval[17:16] 16’hxxxx,user_srval[15:0]
18 4’hx 2’bxx,user_srval[17:16] 16’hxxxx,user_srval[15:0]
16 4’hx 4’hx 16’hxxxx,user_srval[15:0]
10 3’bxxx,user_srval[9] 3’bxxx,user_srval[8] 24’hxxxxxx,user_srval[7:0]
9 4’hx 3’bxxx,user_srval[8] 24’hxxxxxx,user_srval[7:0]
8 4’hx 4’hx 24’hxxxxxx,user_srval[7:0]
5 4’hx 3’bxxx,user_srval[4] 28’hxxxxxxx,user_srval[3:0]
4 4’hx 4’hx 28’hxxxxxxx,user_srval[3:0]
2 4’hx 4’hx 30’hxxxxxxxx,user_srval[1:0]
1 4’hx 4’hx 31’hxxxxxxxx,user_srval[0]
reg_rstval
Thereg_rstvalparameterdefinestheactiveleveloftheoutputregisterrstreginput.Assigning
avalueof1’b0toreg_rstvalconfigurestheoutputregistertohaveanactive‐lowsynchronous
reset, while assigning a value of 1’b1 configures the output register to have an active‐high
synchronousreset.Thedefaultvalueofthere
g_rstvalparameteris1’b1.
regce_priority
Theregce_priorityparameterdefinesthepriorityoftheoutregceclockenableinputrelativeto
the rstreg reset input during an assertion of the rstreg signal on the output register. Setting
regce_priorityto“rstreg”allowstheoutputregister tobe set/resetatthenextactiveedgeof
therdclkwithoutrequiringas
pecificvalueontheoutregceoutputregisterclockenableinput.
Settingregce_priorityto“regce” requiresthattheoutregceoutputregisterclockenableinput
isactivefortheoutputregisterset/resetoperationtooccuratthenextactiveedgeoftherdclk.
wrrst_rstval
The wrrst_ rstval parameter defines the active level of the write port reset (wrrst) input.
Assigning a value of 1’b0 to wrrst_rstval configures the write port reset input to have an
active‐lowsynchronous reset,whileassigninga value of1’b1 configuresthewriteportreset
inputtohaveanactive‐highre
set.Thedefaultvalueofthewrrst_rstvalparameteris1’b1.
wrrst_input_mode
The wrrst_ input_mode parameter defines how the Write Pointer is reset. The FIFO macro
providestheuserwithseveraloptionstoresettheFIFOeithersychronouslyortosynchronize
the reset input to the appropriate clock domain within the FIFO without the need to
implementseparatesynchronizationcircuitryintheFPGAfabric.
The Wr
ite Pointer Reset input of the Write Pointer must be synchronous to the wrclk clock
domain.The user must either provide a synchronous reset via the wrrst or rdrst inpu ts or
synchronize the rdrst input.The method to reset the Write Pointer is selected via the
wrrst_input_mode paramter as defined in Table 6‐26: wrrst_input_mode Parameter
Mapping.
By configuring the wrrst_
input_mode and rdrst_input_mode parameters, the user may
choosetohavetheFIFOWritePointerandReadPointerresetbyoneorbothofthewrrst/rdrst
- Speedster22i 1
- Macro Cell Library 1
- Copyright Info 2
- Table of Contents 3
- Introduction 15
- Cell Naming Conventions 16
- Item Format Examples 17
- Chapter 1 – I/O Cells 18
- Bidirectional I/O Pad 19
- Set/Reset 21
- I/O Cells IOPAD_D 23
- IOPAD_D2 26
- Non-Registered Input Pad 30
- I/O Cells IPAD_D2 36
- IPAD_DIFF 37
- IPAD_DIFFD 39
- IPAD_DIFFD2 41
- I/O Cells IPAD_DIFFD2 43
- Non-Registered Output Pad 44
- I/O Cells OPAD_D 47
- I/O Cells OPAD_D2 50
- OPAD_DIFF 52
- OPAD_DIFFD 54
- I/O Cells OPAD_DIFFD 55
- OPAD_DIFFD2 57
- I/O Cells OPAD_DIFFD2 58
- I/O Cells TPAD_D 63
- Chapter 2 – Registers 65
- Synchronous Clear 69
- Synchronous Preset 71
- Inputs Output 74
- Asynchronous/Synchronous Set 76
- Chapter 3 – Logic Functions 99
- VHDL Instantiation Template 100
- Four Input Lookup Table 101
- Parameters 101
- Name Type Description 103
- Chapter 6 – Memories 106
- BRAM80K Pins 107
- Memories BRAM80K 109
- Read and Write Operations 115
- Timing Diagrams 117
- Memory Initialization 118
- PAGE 102 119
- PAGE 103 120
- PAGE 104 121
- PAGE 105 122
- PAGE 106 123
- PAGE 107 124
- PAGE 108 125
- PAGE 109 126
- PAGE 110 127
- PAGE 118 135
- BRAM80KFIFO 136
- Name Type 137
- Description 137
- Memories BRAM80KFIFO 139
- PAGE 122 139
- PAGE 123 140
- PAGE 124 141
- PAGE 125 142
- PAGE 126 143
- Selected Input for Write 144
- Write Pointer Reset Use Model 144
- PAGE 128 145
- PAGE 129 146
- PAGE 130 147
- PAGE 131 148
- PAGE 132 149
- Read and Write Count Outputs 150
- Status Flags 151
- Flag Latency 152
- Optional Output Register 153
- FIFO Operational Modes 154
- FIFO Operations 155
- PAGE 140 157
- BRAM80KECC 164
- BRAM80KECC Pins 165
- Memories BRAM80KECC 166
- PAGE 149 166
- PAGE 150 167
- BRAM80KECC Modes of Operation 168
- BRAM80KECCFIFO 170
- LRAM640 Pins 174
- Memories LRAM640 175
- PAGE 158 175
- LRAM640 Memory Initialization 176
- LRAMFIFO 177
- parameteris7’h04, 181
- Write Error Flag 183
- Read Error Flag 183
- Chapter 7 – Multipliers 188
- Inputs Outputs 189
- BMACC56 Pins 190
- Multipliers BMACC56 193
- PAGE 176 193
- PAGE 177 194
- PAGE 178 195
- PAGE 179 196
- PAGE 180 197
- PAGE 181 198
- PAGE 182 199
- BMULT28X28 200
- Chapter 8 – Special Functions 201
- ACX_DESERIALIZE 203
- Speedster Macro Cell Library 204
- PAGE 187 204
- ACX_CLKGEN 205
- ACX_CLKGEN Pins 206
- Default 208
- ACX_CLKGEN Components 211
- Feedback Divider 212
- Clock Feedback Selection 212
- PLL Control 213
- Serial Control Bus (SCB) 213
- PAGE 197 214
- PAGE 198 215
- PAGE 199 216
- PAGE 200 217
- PAGE 201 218
- PAGE 202 219
- PAGE 203 220
- PAGE 204 221
- PAGE 206 223
- Revision History 224
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