
I/O Cells IOPAD_D2
Speedster Macro Cell Library
www.achronix.com PAGE 9
IOPAD_D2
Bidirectional DDR I/O Pad with Asynchronous or Synchronous Set/
Reset
q
ce
d
rstn
q
ce
d
rstn
srstn
oerstn
douta
pad
Note: For Speedster22iHP, txdata_en and rxdata_en are shared.
For Speedster22iHD, txdata_en and rxdata_en may be driven separately.
IOPAD_D2
q
ce
d
rstn
q
ce
d
rstn
srstn
q
d
rstn
q
d
rstn
q
d
rstn
q
d
rstn
q
d
rstn
q
d
rstn
q
ce
d
rstn
srstn
q
ce
d
rstn
srstn
oe
txclk
txrstn
dina
dinb
txdata_en
txclk
rxdata_en
rxrstn
srstn
rxclk
doutb
Figure 1-3: IOPAD_D2 Logic Symbol
IOPAD_D2 is aDoubl
eDataRate (DDR) I/Opadwith active‐highregisteredoutput enable.
Thereisanadditionalstageofregistersontheinputsandoutputstoallow thelogiclevelon
the pad tochangesonboth therisingandfalling edges of theclock,butallow the interface
signalstoandfromtheFP
GAcoretochangeontherisingedgeoftheclock. Thisadditional
levelofregistersprovidesafullcycletogetintoandoutoftheFPGAcore.
P
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