
I/O Cells IOPAD_D
Speedster Macro Cell Library
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IOPAD_D
Bidirectional Registered I/O Pad with Asynchronous or Synchronous
Set/Reset
q
ce
d
rstn
q
ce
d
rstn
srstn
q
ce
d
rstn
srstn
txrstn
rxrstn
oerstn
din
dout
pad
oe
txclk
rxclk
oeclk
txdata_en
rxdata_en
srstn
Note: For Speedster22iHP, txdata_en and rxdata_en are shared.
For Speedster22iHD, txdata_en and rxdata_en may be driven separately.
IOPAD_D
Figure 1-2: IOPAD_D Logic Symbol
IOPAD_DisanI/
Opadwhereeachofthetransmit,receive,oroutputenableregistersmaybe
bypassed.Theinput,output,andoutputenableregistersareallclockedontherisingedgeof
theirrespectiveclocks.Theactive‐highoeregisterisasynchronouslycleareduponalowonthe
oerstninput.Drivingrxrstnlowperf
ormsanasynchronousinitializationoftheinputregister.
The value initialized into the input register is determined by the value of the rstvalue
parameter.Similarly,drivingtxrstnlowperformsanasynchronousinitializationoftheoutput
register. The value initialized into the output register is also determined by the va
lue of the
rstvalueparameter.Drivingsrstnlowperformsasynchronousinitializationofboththeinput
and output registers if the rstmode parameter is set toʺsyncʺ. The value initialized into the
inputandoutputregistersisalsodeterminedbythevalueoftherstvalueparameter.Whenthe
rstmodepa
rameterissettoʺsyncʺ,theinputandoutputregistershavetheirsynchronousreset
inputs active. The synchronous and asynchronous reset capability of the input and output
registersismutuallyexclusive.Theinputandoutputregisterscanbothhaveasynchronousor
bothhaveasychronousresetsasselectedbytherstm
odeparameter.
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