Achronix Speedster22i User Macro Guide Manuale Utente Scaricare il pdf (Pagina 85)

Registers DFFNER

Speedster22i Macro Cell Library

AchronixSemiconductorProprietary PAGE 69

DFFNER

Negative Clock Edge D-Type Register with Clock Enable and

Asynchronous/Synchronous Reset

ckn

DFFNER

Figure 2-10: Logic Symbol

DFFNER is a si

ngle D‐type register with data input (d), clock enable (ce), clock (ckn), and

active‐lowreset(rn)inputsanddata(q) output.Theactive‐lowresetinputoverridesallother

inputs when it is asserted low and sets the data output low. The resonseof the q output  in

sponse to the asserted reset depends on the value of the sr_assertion parameter and is

detailedinTable2‐32

: DFFNERFunctionTablewhensr_assertion=“unclocked”andTable

2‐33: DFFNER Function Table wh

en sr_assertion = “clocked”. If the reset input is not

asserted,thedataoutputissettotheva

lueonthedatainputuponthenextfallingedgeofthe

clockiftheactive‐highclockenableinpu tisasserted.

Pins

Table 2-30: Pin Descriptions

Name Type Description

d Data input.

Active-low asynchronous/sy

nchronous reset input. A low on rn sets the

q output low independent of the other inputs if the sr_assertion parame-

ter is set to “unclocked”. If the sr_assertion parameter is set to “clocked”, a

w on rn sets the q output low at the next falling edge of the clock.

ce Active-high clock enable input.

ckn Negative-edge clock input.

Data output. The value pr

esent on the data input is transferred to the q

output upon the falling edge of the clock if the clock enable input is high

and the reset input is high.

Parameters

Table 2-31: Parameters

Parameter Defined Values Default Value

init 1’b0

sr_assertion “unclocked”

init

Theinitparameterdefinestheinitialvalueoftheoutput oftheDFFNERregister.Thisisthe

valuetheregistertakesupontheinitialapplicationofpowertotheFPGA.Thedefaultvalue

oftheinitparameteris1’b0.

input

output

1’b0, 1’b1

“unclocked”, “clocked”

1 2 ... 80 81 82 83 84 85 86 87 88 89 90 ... 223 224

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