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UG018, April 15, 2013

Synthesis User Guide

Introduction

This User Guide describes how to use Synplify Pro from Synopsys to synthesize a design and

generate a netlist for implementation on an Achronix Speedster22i HD device. Suggested

Optimization Techniques are also included.

Synplify-Pro reads in standard RTL and outputs a Mapped netlist which is used by the

Achronix CAD Environment (ACE) tool. The netlist file uses a .vma extension.

A high level overview of the Achronix design flow is shown in Figure 1 below.

Figure 1 – Synthesis Flow

RTL Design

Mapped Netlist

Synthesis using

Synplify Pro

Place and Route

ACE

Bitstream Generation

If Timing

Not Met

1 2 3 4 5 6 7 8 ... 16 17

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Achronix Synthesis Manuale Utente Pagina 3