2 UG018, April 15, 2013
Table of Contents
Introduction ....................................................................................................... 3
Synplify Pro Introduction .................................................................................. 4
Resource Sharing .......................................................................................................................... 6
Verilog ............................................................................................................................................ 6
Place and Route ............................................................................................................................ 7
Timing Report ................................................................................................................................ 7
Implementation Result ................................................................................................................... 7
Constraints ..................................................................................................................................... 7
Options .......................................................................................................................................... 7
Synthesis Optimization Recommendations .................................................... 8
Hanging Nets ......................................................................................................................... 8
Clock Constraints ................................................................................................................... 9
Pipelining ............................................................................................................................... 9
Retiming ................................................................................................................................. 9
Memories ............................................................................................................................. 10
Block RAM (BRAM) ...................................................................................................................... 10
Local Ram (LRAM) ....................................................................................................................... 12
Finite State Machines .......................................................................................................... 12
Finite State Machine (FSM) Compiler........................................................................................... 12
Replication of States that have high fan-ins ................................................................................. 13
Example Synplify-Pro Project File ................................................................. 15
Revision History .............................................................................................. 17
(13 pagine)
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