Achronix Speedster22i SerDes Manuale Utente Scaricare il pdf (Pagina 12)

SerDes Architecture Overview

The SerDes has an independent lane architecture. Each lane has a Physical Media Attachment

(PMA), Synthesizer (Transmit PLL), Clock and Data Recovery (CDR) and Physical Coding

Sublayer (PCS). The Receiver PMA and Transmitter PMA block diagrams are shown in

“Figure 2: SerDes Architecture” below.

Figure 2: SerDes Architecture

The SerDes primarily consists of the following blocks:

• PMA

• PCS

• PCS interface to FPGA fabric

• Clocking

• Debug and Test

12 UG028, July 1, 2014

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Speedster22i SerDes 1
User Guide 1
Table of Contents 2
4 UG028, July 1, 2014 4
List of Figures 5
List of Tables 6
Overview 7
Major standards supported 9
10 UG028, July 1, 2014 10
SerDes Placement 11
SerDes Architecture Overview 12
1. Common 13
3. Digital PMA (DPMA) 14
PCS Self Test Logic 16
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Interface Encapsulation 20
8b/10b Encoder 20
Running Disparity 20
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Polarity Bit Reversal (PBR) 23
Symbol Alignment 23
Modes of Operation 24
Manual Mode: 24
Bit Slip Mode: 24
Automatic Mode: 24
Deskew FIFO 25
Functional Description 26
Auto Mode: 26
Symbol slip mode: 27
28 UG028, July 1, 2014 28
EFIFO Operation 29
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8b/10b Decoder 31
Bit Slider 31
PCS Self Test Checker 32
PCS Interface 33
PIPE Interface 34
Clocking 36
Debug and Test 38
PMA loopback modes: 39
PCS loopback modes: 39
PMA Test Pattern Generator 40
PMA Test Pattern Checker 40
PCS Test Pattern Generator 40
PRBS Generator 40
PCS Test Pattern Checker 41
Latency 42
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Configurations Supported 45
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48 UG028, July 1, 2014 48
Single-Lane Serdes Wrapper 50
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Overview Section: 53
Entry field 54
Purpose 54
Available Options 54
Choice made 54
56 UG028, July 1, 2014 56
Section on PMA Settings: 57
58 UG028, July 1, 2014 58
RX PMA Equalization 59
RX PMA PLL 60
TX PMA Driver 62
TX PMA PLL 62
Section on PCS Settings: 63
RX PCS Settings 64
RX PCS Symbol Alignment 66
TX PCS Settings 68
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Files Generated by ACE-GUI 71
Design and Wrapper Files 72
Sequence 74
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Placement of SerDes 77
Timing Constraints 78
Design Guidelines 80
Figure 37: Clock Region View 82
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Wide Bus 86
Design Tips 87
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Design Bypassing PCS: 93
Modification – 1 (ACE GUI): 94
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ACX_SERDES_SBUS_IF Module 99
General signals: 100
SerDes signals: 100
Parallel Interface signals: 100
UG028, July 1, 2014 101
Pass-through signals: 102
Loopback Modes 102
SerDes signals 102
Control signals 102
SerDes Registers 103
Electrical Specifications 104
Transmitter 105
106 UG028, July 1, 2014 106
Receiver 108
Eye Diagram 110
Reference Clock 112
Revision History 113

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