Achronix Speedster22i HD1000 Development Kit User Guide Manuale Utente Pagina 51
- Pagina / 69
- Indice
- RISOLUZIONE PROBLEMI
- SEGNALIBRI
- ACX-KIT-HD1000-100G 1
- Development Kit 1
- User Guide 1
- Copyright Info 2
- Table of Contents 3
- 4 UG034, July 1, 2014 4
- List of Figures 6
- List of Tables 7
- Preface 8
- Reference Documents 9
- Overview 10
- Interfaces 11
- Controller 12
- Additional memories 12
- UG034, July 1, 2014 13
- Use Modes 14
- On-Board Memory 15
- On-Board Controller 15
- Board-Specific Design Issues 16
- Running the software 18
- Standalone Mode 18
- Standalone Board Connections 19
- In-System Board Connections 20
- Shunt Position 22
- Configuration Mode 22
- Bitstream Source 22
- HD1000 (U33) 22
- Connection 22
- FLASH Programming 24
- Chapter 4 – Interfaces 25
- HD1000 FPGA Interfaces 26
- 28 UG034, July 1, 2014 28
- Signal Name 29
- SerDes No 29
- Pin on HD1000 (U33) 29
- 30 UG034, July 1, 2014 30
- FMC Expansion Port (HPC, J3) 32
- Pin on Connector (J3) 33
- System Interfaces 37
- USB (U54, U41) 38
- JTAG (J11) 39
- Controller Interfaces 40
- Memory Interfaces 40
- One DDR3 Device (U21) 41
- RLDRAM3 Devices (U31, U36) 42
- Pin on MT44K32M18RB 43
- QDR2+ Device (72 Mb) 45
- Pin on CY7C2565XV18 (U22) 46
- User Interfaces 48
- SMA Connectors 49
- 50 UG034, July 1, 2014 50
- Switch (SW7) 51
- Chapter 5 – Clocking 52
- Pin on ICS853310 (U72) 54
- PLL (U33) 54
- MAX6642 (U37) 55
- Atmega2560 (U35) 55
- 58 UG034, July 1, 2014 58
- 60 UG034, July 1, 2014 60
- Switches 62
- Jumpers 63
- Implementation 64
- Connected 64
- Function 64
- Appendix C – Troubleshooting 68
- Version 69
- Revisions 69
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