Achronix Speedster22i DDR Manuale Utente Scaricare il pdf (Pagina 22)

DDR Interface

Logic

(User RTL)

Speedster22i

DDR

Controller

ddr_int_wr_request

ddr_int_addr[33:0]

ddr_int_burst_size[7:0]

ddr_int_busy_align

ddr_int_wrdata_req_early_align

ddr_int_wrdata_req_align

ddr_int_wrdata[575:0]

ddr_int_writedata_mask[35:0]

clk_div4

Figure 10: Write Interface with Wide Bus Interface Enabled

The following timing diagram illustrates a single write command of burst length 4. The

signals shown in the following diagrams are ports at the (‘ddr3_xSIZE

_LOCATION

’. Where

1: SIZE = 72, 64, 32, 16, 8 and 2: LOCATION=EN, EC, ES, WN, WC, WS).

ddr_int

_ wrdata_req_early_

align

Clk_div4

ddr_int_wr_

request

ddr_

int_addr[

33:0

]

ddr_int_busy_align

ddr_int_wrdata_req

ddr_int_wrdata[575:0]

Valid Write commands

ddr_int

_burst_size[7:0]

Timing relationship between ddr_int_wr_request assertion and

ddr_int_

wrdata_req assertion between AL/CWL configurations settings/refresh

status, and status of bank/row being accessed

Present data 1 cycle after

ddr_int_wrdata_req

_early_align is asserted

Figure 11: Internal Interface Write Protocol Timing Diagram with Wide Bus Interface Enabled

22 UG031, Nov 18, 2014

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 31 32

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